• entity - объявление входов и выходов модуля
• architecture - описание внутренней структуры модуля и его поведения.

entity entity_name is
  port (signal_names: mode signal_type;
	      signal_names: mode signal_type;
	      signal_names: mode signal_type);
end entity_name;

Entity:
entity Inhibit is        -- Comments
  port (X,Y : in BIT;
        Z   : out BIT);
end Inhibit;

• entity_name - имя объекта
• signal_names - список внешних сигналов
• mode - направление передачи сигнала
  • in - входной сигнал
  • out - выходной сигнал, не доступен внутри объекта.
  • buffer - выходной сигнал, но доступен внутри объекта.
  • inout - вывод с 3-мя состояниями.
• signal_type - тип сигнала

architecture architecture_name of entity_name is
  type declarations
  signal declarations
  constant declarations
  function declarations
  procedure declarations
  component declarations
begin
  concurrent_statement;
  concurrent_statement;
  ...
  concurrent_statement;
end architecture_name;

architecture Inhibit_arch of Inhibit is
begin
  Z <= '1' when X = '1' and Y = '0' else '0';
end Inhibit_arch

Тело архитектуры представляет собой ряд параллельных операторов - concurrent_statement. Все параллельные операторы в теле архитектуры исполняются одновременно!

Самым главным параллельным оператором является оператор component. Для каждого оператора component в теле архитектуры создается копия объекта, которая должна иметь уникальную метку label.

label: component_name port map(signal1, signal2, ... signalN);
label: component_name port map(port1=>signal1, port2=>signal2, ... portN=>signalN);

bit, bit_vector, boolean, character, integer, real, severity_level, string, time

type STD_ULOGIC is (
                    'U',   -- Uninitialized
                    'X',   -- Forcing Unknown
                    '0',   -- Forcing 0
                    '1',   -- Forcing 1
                    'Z',   -- High Impedance
                    'W',   -- Weak Unknown
                    'L',   -- Weak 0
                    'H',   -- Weak 1
                    '-',   -- Don't Care
                    );

subtype STD_LOGIC is resolved STD_ULOGIC;
type STD_LOCIC_VECTOR is array (natural range <>) of STD_LOGIC;  -- безразмерный массив

subtype natural is integer range 0 to highest-integer;
subtype positive is integer range 1 to highest-integer;

type type_name is (value_list)
subtype subtype_name is type_name start to end;
subtype subtype_name is type_name start downto end;

constant constant_name: typename := value;

type type_name is array (start to end) of element_type;
type type_name is array (start downto end) of element_type;
type type_name is array (range_type) of element_type;
type type_name is array (range_type range start to end) of element_type;
type type_name is array (range_type range start downto end) of element_type;

B := ('1', '0', '0', '1', '1', '1', '0', '1');  -- Массивы литералы
B := (1=>'0', 5=>'0', 6=>'0', others=>'1');     -- Тоже самое

type traffic_light_state is (reset, stop, wait, do);

subtype twoval_logic is std_logic range '0' to '1';
subtype fourval_logic is std_logic range 'X' to 'Z';
subtype negint is integer range -2147483647 to '-1';
subtype bitnum is integer range 31 downto 0;

constant BUS_SIZE: integer := 32;      -- bus width
constant MSB: integer := BUS_SIZE-1;   -- bit number of MSB
constant Z: character := 'Z';          -- synonym for Hi-Z value

type byte is array (7 downto 0) of STD_LOGIC;
constant WORD_LEN: integer := 32;
type word is array (WORD_LEN-1 downto 0) of STD_LOGIC;
type statecount is array (traffic_light_state) of integer;

• +, -, *, / - сложение, вычитание, умножение, деление
• mod - деление по модулю
• rem - остаток от деления по модулю
• abs - абсолютное значение
• ** - возведение в степень

• and - И
• or - ИЛИ
• nand - И-НЕ
• nor - ИЛИ-НЕ
• xor - Исключающее ИЛИ
• xnor - Исключающее ИЛИ-НЕ
• not - инверсия

function function_name (
    signal_names: signal_type;
    ...
    signal_names: signal_type
) return return_type is
  type declarations
  constant declarations
  function definitions
  procedure definitions
begin
  sequential_statement;
  sequential_statement;
  ...
  sequential_statement;
end function_name;

architecture Inhibit_archf of Inhibit is
  functino ButNot(A,B: bit) return bit is
  begin
    if B = '0' then return A;
    else return '0';
    endif;
  end ButNot
begin
  Z <= ButNot(X,Y);
end Inhibit_archf

function CONV_INTEGER (X: STD_LOGIC_VECTOR) return INTEGER is
  variable RESULT: INTEGER;
begin
  RESULT := 0;
  for i in X'range loop
    RESULT := RESULT*2;
    case X(i) is
      when '0' | 'L' => null;
      when '1' | 'H' => RESULT := RESULT + 1;
      when others => null;
    end case
  end loop;
  return RESULT;
end CONV_INTEGER;

function CONV_STD_VECTOR(ARG: INTEGER; SIZE: INTEGER) 
  return STD_LOGIC_VECTOR is
  variable result: CONV_STD_VECTOR(SIZE-1 downto 0);
  variable temp: integer;
begin
  temp := ARG;
  for i in 0 to SIZE-1 loop
    if (temp mod 2) = 1 then result(i) := '1';
    else result(i) := '0';
    end if;
    temp := temp / 2;
  end loop;
end CONV_STD_VECTOR;

При создании проекта автоматически создается библиотека work, неявно в начале файла помещается "library work;". Можно поменять - library (library_clause), например library ieee;

Package - файл, содержащий определения элементов, которые могут быть использованы другими программами. Пакет может включать сигналы, типы, константы, функции, процедуры, объявления компонентов.

Подключение пакета, всего или отдельного определения:

use ieee.std_logic1164.all;
use ieee.std_logic1164.std_ulogic;

• ieee - библиотека
• std_logic1164 - файл в библиотеке
• all или std_ulogic - определения в этом файле.

package package_name is
  type declarations         -- Объявления доступные снаружи пакета
  signals declarations
  constant declarations
  component declarations
  function declarations
  procedure declarations
end package_name;

package body package_name is
  type declarations         --   Локальные объявления, видны только внутри
  constant declarations
  function definitions
  procedure definitions
end package_name;

component component_name
  port (signal_name: mode signal_type;)
        signal_name: mode signal_type;)
        ...
        signal_name: mode signal_type;)
end component;

library IEEE;
use IEEE.std_logic_1164.all;

entity prime is
  port (N: in STD_LOGIC_VECTOR (3 downto 0);
        F: out STD_LOGIC);
end prime;

architecture prime1_arch of prime is
signal N3_L, N2_L, N1_L: STD_LOGIC;
signal N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
component INV port (I: in STD_LOGIC, O: out STD_LOGIC); end component;
component AND2 port (I0,I1: in STD_LOGIC, O: out STD_LOGIC); end component;
component AND3 port (I0,I1,I2: in STD_LOGIC, O: out STD_LOGIC); end component;
component OR4 port (I0,I1,I2,I3: in STD_LOGIC, O: out STD_LOGIC); end component;
begin
  U1: INV  port map (N(3), N3_L);
  U2: INV  port map (N(2), N2_L);
  U3: INV  port map (N(1), N1_L);
  U4: AND2 port map (N3_L, N(0), N3L_N0);
  U5: AND3 port map (N3_L, N2_L, N(1), N3L_N2L_N1);
  U6: AND3 port map (N2_L, N(1), N(0), N2L_N_N0);
  U7: AND3 port map (N(2), N1_L, N(0), N2_N1L_N0);
  U8: OR4  port map (N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0, F);
end prime1_arch;

library IEEE;
use IEEE.std_logic_1164.all;

entity businv is
  generic (WIDTH: positive);
  port(X: in STD_LOGIC_VECTOR (WIDTH-1 to 0);
       Y: out STD_LOGIC_VECTOR (WIDTH-1 to 0) );
end businv;

architecture businv_arch of businv is
component INV port(I: STD_LOGIC; O: out STD_LOGIC); end component;
begin
  g1: for b in WIDTH-1 downto 0 generate
    U1: INV port map(X(b), Y(b));
    end generate;
end businv_arch;

Использование:

library IEEE;
use IEEE.std_logic_1164.all;

entity businv_example is
  port(IN8: in STD_LOGIC_VECTOR (7 to 0);
       OUT8: out STD_LOGIC_VECTOR 7 to 0);
       IN16: in STD_LOGIC_VECTOR (15 to 0);
       OUT16: out STD_LOGIC_VECTOR 15 to 0);
       IN32: in STD_LOGIC_VECTOR (32 to 0);
       OUT32: out STD_LOGIC_VECTOR (32 to 0) );
end businv_example;

architecture businv_ex_arch of businv_example is
component businv 
  generic (WIDTH: positive);
  port(X: in STD_LOGIC_VECTOR (WIDTH-1 to 0);
       Y: out STD_LOGIC_VECTOR (WIDTH-1 to 0) );
end component;
begin
U1: businv generic map (WIDTH=>8) port map (IN8, OUT8);
U2: businv generic map (WIDTH=>16) port map (IN16, OUT16);
U3: businv generic map (WIDTH=>32) port map (IN32, OUT32);
end businv_ex_arch;

Это Описание схемы в терминах потока данных и выполняемых схемой операций над этими данными.

Параллельный сигнальный оператор присваивания:

signal_name <= expression;
signal_name <= expression when boolean_expression else
               expression when boolean_expression else
               ...
               expression;

Пример проверки на простое число:

architecture prime2_arch of prime is
signal N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
  N3L_N0     <= not N(3)                           and N(0);
  N3L_N2L_N1 <= not N(3) and not N(2) and     N(1)         ;
  N2L_N1_NO  <=              not N(2) and     N(1) and N(0);
  N2_N1L_N0  <=                  N(2) and not N(1) and N(0);
  F <= N3L_N0 or N3L_N2L_N1 or N2L_N1_NO or N2_N1L_N0;
end prime2_arch;

или с условиями

architecture prime3_arch of prime is
signal N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
  N3L_N0     <= '1' when N(3)='0' and N(0)='1' else 0;
  N3L_N2L_N1 <= '1' when N(3)='0' and N(2)='0' and N(1)='1' else 0;
  N2L_N1_NO  <= '1' when N(2)='0' and N(1)='1' and N(0)='1' else 0;
  N2_N1L_N0  <= '1' when N(2)='1' and N(1)='0' and N(0)='1' else 0;
  F <= N3L_N0 or N3L_N2L_N1 or N2L_N1_NO or N2_N1L_N0;
end prime3_arch;

или с использованием select

architecture prime4_arch of prime is
begin
  with N select
  F <= '1' when "0001",
       '1' when "0010",
       '1' when "0011" | "0101" | "0111",
       '1' when "1011" | "1101",
       '0' when others;
end prime4_arch;

или с использованием конвертации в Integer

architecture prime5_arch of prime is
begin
  with CONV_INTEGER(N) select
  F <= '1' when 1 | 2 | 3 | 5 | 7 | 11 | 13,
       '0' when others;
end prime5_arch;

process (signal_name, ... signal_name)
  type declarations
  variable declarations     -- вместо сигналов, локальная видимость
  constant declarations
  function definitions
  procedure definitions
begin
  sequential_statement;
  ...
  sequential_statement;
end process;

Процесс всегда либо выполняется, либо приостановлен. Перечень сигналов (sensitivitty_list) задает условия, когда процесс выполняется. Первоначально процесс остановлен.

ОПЕРАТОРЫ выполняются внутри ПРОЦЕССА ПОСЛЕДОВАТЕЛЬНО! Оператор ⇐ в процессе - это последовательный оператор присваивания! Для переменных это оператор := .

variable ariable_name: vatiable_type;

signal_name <= expression
variable_name := expression

Пример:

architecture prime6_arch of prime is
begin
  process(N)
    variable N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
  begin
    N3L_N0     := not N(3)                           and N(0);
    N3L_N2L_N1 := not N(3) and not N(2) and     N(1)         ;
    N2L_N1_NO  :=              not N(2) and     N(1) and N(0);
    N2_N1L_N0  :=                  N(2) and not N(1) and N(0);
    F <= N3L_N0 or N3L_N2L_N1 or N2L_N1_NO or N2_N1L_N0;
  end process;  
end prime6_arch;

тоже с приведением к Integer

architecture prime7_arch of prime is
begin
  process(N)
    variable NI: INTEGER;
  begin
    NI = CONV_INTEGER(N);
    if NE=1 or NI=2 then F <= '1';
    elsif NI=3 or NI=5 or NI=7 or NI=11 or NI=13 then F <= '1';
    else F <= '';
    end if;
  end process;  
end prime7_arch;

тоже с оператором выбора

case expression is
  when choises => sequential_statement;
  ...
  when choises => sequential_statement;
end case

architecture prime8_arch of prime is
begin
  process(N)
    variable NI: INTEGER;
  begin
    case CONV_INTEGER(N) is
      when 1 => F <= '1';
      when 2 => F <= '1';
      when 3 | 5 | 7 | 11 | 13  => F <= '1';
      when others F <= '0';
    end case;
  end process;  
end prime8_arch;

loop
  sequential_statement;
  ...
  sequential_statement;
end loop;

for identifier in range loop
  sequential_statement;
  ...
  sequential_statement;
end loop;

exit - выход на след. оператор после цикла.
next - переход на след итерацию в цикле.

while boolean_expression loop
  sequential_statement;
  ...
  sequential_statement;
end loop;

Задержка 4нс при переходе выхода из 0 в 1, и 3нс при переходе из 1 в 0:

Z <= '1' after 4 ns when X='1' and Y='0' else '0' after 3ns;

entity InhibitTestBench is
end InhibitTestBench;

architecture InhibitTestBench_arch of InhibitTestBench is
component Inhibit port (X,Y: in BIT; Z: out BIT); end component;
signal XT,YT,ZT: BIT;
begin
  U1: Inhibit port map (XT,YT,ZT);
  process
  begin
    XT<= '0'; XT <= '0';
    wait for 10 ns;
    XT<= '0'; XT <= '1';
    wait for 10 ns;
    XT<= '1'; XT <= '0';
    wait for 10 ns;
    XT<= '1'; XT <= '1';
    wait;                 -- безусловная остановка процесса
  end process;
end InhibitTestBench_arch;